library ieee;
use ieee.std_logic_1164.all;

entity pract2 is
port(A,B,C,D,E:in std_logic;
	F:out std_logic);
end pract2;


architecture bhv of pract2 is
signal temp:std_logic_vector(4 downto 0);
begin

temp<=A&B&C&D&E;

with temp select
	F<='1' when "00000",
		'1' when "00011",
		'1' when "00101",
		'1' when "00111",
		'1' when "01000",
		'1' when "01001",
		'1' when "10100",
		'1' when "11101",
		'1' when "11110",
		'0' when others;
end bhv;